Charge pump circuit, phase locked loop apparatus, integrated circuit, and method of manufacture of a charge pump

ABSTRACT

A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

FIELD OF THE INVENTION

This invention relates to a charge pump circuit, a phase locked loopapparatus, and integrated circuit and a method of manufacture of acharge pump.

BACKGROUND OF THE INVENTION

The use of Phase Locked Loop (PLL) circuits in electronic circuits iswidespread throughout the field of electronics. For radar applications,particularly but not exclusively in the automotive industry, users ofthe PLLs in a radar device require particular operational parameters inorder to achieve certain operational goals using the radar device. Inthis respect, known existing XOR-PLLs are designed for so-called LongRange Radar (LRR) applications where output signal modulation isrelatively slow. However, as the modulation speed increases, phase noiseof the radar device becomes increasingly important, because the phasenoise affects noise density at a receiver IF output of the radar device.In this respect, so-called Short Range Radar (SRR) radar transmittersoperate at a higher modulation frequency than LRR radar transmitters,for example 38 GHz vs. 77 GHz. Furthermore, radar devices can berequired to support both LRR and SRR functionality and for suchrequirements, the Voltage Controlled Oscillator (VCO) of the PLL of theradar device requires a large frequency tuning range, for example around10 GHz, at a relatively high tuning range voltage, for example around5V.

In order to satisfy such performance requirements, the PLL can be aso-called charge pump PLL. However, a charge pump PLL comprising acharge pump formed solely from Field Effect Transistor (FET) devices isunable to satisfy the above-mentioned performance requirements due tothe fact that the FET devices have limited switching speeds and requirea standard supply voltage. Bipolar-Complementary Metal OxideSemiconductor (BICMOS) circuits are known to overcome such encumbrances,but known BICMOS charge pump circuits nevertheless suffer from limitedupper frequency range responses due to current derivation on the supplyand ground of the charge pump circuit taking time to settle to a steadystate.

SUMMARY OF THE INVENTION

The present invention provides a charge pump circuit, a phase lockedloop apparatus, and integrated circuit and a method of manufacture of acharge pump as described in the accompanying claims.

Specific embodiments of the invention are set forth in the dependentclaims.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details, aspects and embodiments of the invention will bedescribed, by way of example only, with reference to the drawings. Inthe drawings, like reference numbers are used to identify like orfunctionally similar elements. Elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 is a schematic block diagram of a charge pump phase locked loop;

FIG. 2 is a schematic circuit diagram of a charge pump circuit anddriving stage circuit used by a charge pump block of FIG. 1 andconstituting an example of the present invention; and

FIG. 3 is a schematic circuit diagram of current sources of the chargepump circuit of FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Because the illustrated examples may for the most part, be implementedusing electronic components and circuits known to those skilled in theart, details will not be explained in any greater extent than thatconsidered necessary, for the understanding and appreciation of theunderlying concepts of the examples set forth herein and in order not toobfuscate or distract from the teachings herein.

According to a first example, there may be provided a charge pumpcircuit that may comprise: a first bipolar transistor device and asecond bipolar switching device arranged in a differential pairconfiguration; a first terminal of each of the first and second bipolarswitching devices may be coupled to a voltage supply; a second liketerminal of each of the first and second bipolar switching devices maybe coupled together and to ground potential via a pulsed current source;and a field effect switching device; wherein the first terminal of thefirst bipolar switching device may be coupled to the voltage supply viathe field effect switching device.

The first terminal of the second bipolar switching device may be coupledto the voltage supply via a low pass filter.

The first terminal of the first bipolar switching device may also becoupled to the supply via another current source.

The field effect switching device may be coupled to the voltage supplyvia the another current source.

The first and second bipolar switching devices may each comprise acontrol terminal, together constituting differential control terminals.

According to a second example, there may be provided a charge pumpapparatus that may comprise: the charge pump circuit as set forth abovein relation to the first example; and a driving stage circuit that maybe coupled to the charge pump circuit and arranged to translate, when inuse, an emitter coupled logic signal to a ground-referenced signal.

The driving stage circuit may comprise a buffer circuit.

The driving stage circuit may comprise a ground-reference signalgeneration circuit coupled to the buffer circuit.

The driving stage circuit may comprise an amplifier circuit coupled tothe ground-reference signal generation circuit.

According to a third example, there may be provided a phase locked loopthat may comprising the charge pump circuit as set forth above inrelation to the first example.

According to a fourth example, there may be provided a phase locked loopapparatus comprising the charge pump apparatus as set forth above inrelation to the second example.

The apparatus may further comprise: a phase and frequency detectorcoupled to the driving stage circuit.

The apparatus may further comprise: a low-pass filter coupled to thecharge pump circuit and a voltage controlled oscillator.

The apparatus may further comprise: a static frequency divider coupledto the voltage controlled oscillator.

The apparatus may further comprise: a programmable frequency divider; adigital controller that may have a reference frequency input and acontrol output; the control output may be coupled to the programmablefrequency divider; wherein the programmable frequency divider may becoupled between the static frequency divider and the phase and frequencydetector.

The apparatus may further comprise: a reference frequency generatorcoupled to the digital controller and the phase and frequency detector.

The reference frequency generator may be coupled to the phase andfrequency detector via a frequency divider.

According to a fifth example, there may be provided a radar apparatuscomprising: the charge pump circuit as set forth above in relation tothe first example or the charge pump apparatus as set forth above inrelation to the first example or the phase locked loop apparatus as setforth above in relation to the fourth example.

According to a sixth example, there may be provided an integratedcircuit comprising the charge pump circuit as set forth above inrelation to the first example or the charge pump apparatus as set forthabove in relation to the first example or the phase locked loopapparatus as set forth above in relation to the fourth example.

According to a seventh example, there may be provided a method ofmanufacturing a charge pump circuit, the method may comprise: providingand arranging a first bipolar transistor device and a second bipolarswitching device in a differential pair configuration; coupling a firstterminal of each of the first and second bipolar switching devices to avoltage supply; coupling a second like terminal of each of the first andsecond bipolar switching devices together and to ground potential via apulsed current source; and coupling the first terminal of the firstbipolar switching device to the voltage supply via a field effectswitching device.

Referring now to FIG. 1, a Phase Locked Loop (PLL) apparatus 100 maycomprise a voltage controlled oscillator 102 coupled to a loop low-passfilter 104 and a buffer 106. The buffer 106 may be coupled to a staticfrequency divider 108; the static frequency divider 108 may be coupledto a programmable frequency divider 112 via another buffer 110. Theprogrammable frequency divider 112 may be coupled to a phase andfrequency detector 114, a logic converter 116 and a digital controller118. The digital controller 118 may comprise a sigma delta modulator120, for example a 20 bit sigma delta modulator, and a ramp signalgenerator 122. The logic converter 116 may be coupled to each of thesigma delta converter 120 and the ramp signal generator 122. The sigmadelta modulator 120 may be coupled to the programmable frequency divider112, constituting the coupling of the digital controller 118 to theprogrammable frequency divider 112. The ramp signal generator 122 may becoupled to the signal delta modulator 120.

The digital controller 118 may also be optionally coupled to a referenceoscillator 124 via an Automatic Level Control (ALC) unit 126 and adifferential-to-single signal converter 128. The ALC unit 126 may becoupled to an input of the reference oscillator 124 and optionally tothe digital controller 118 as described above. An output of thereference oscillator 124 may be coupled to the differential-to-singlesignal converter 128 and the differential-to-single signal converter 128may be coupled to the digital controller 118 as described above.

The reference oscillator 124 may comprise a crystal oscillator 130. Thereference oscillator 124 may be coupled to the phase and frequencydetector 114 via a divide-by-two frequency divider 132. The phase andfrequency detector 114 may be coupled to the loop low-pass filter 104via a charge pump apparatus 134.

Turning to FIG. 2, the charge pump apparatus may comprise a drivingstage circuit 200 and a charge pump circuit 202. The driving stagecircuit 200 may comprise a first differential down signal input 204 anda second differential down signal input 206. The first down signal input204 may be coupled to a first differential down signal output (notshown) of the phase and frequency detector 114 and the second downsignal input 206 may be coupled to a second differential down signaloutput (not shown) of the phase and frequency detector 114. The firstdown signal input 204 may be coupled to a first resistance 208 and thesecond down signal input 206 may be coupled to a second resistance 210.The first resistance 208 may be coupled to a base terminal of a firstNPN bipolar transistor 212 and the second resistance 210 may be coupleda base terminal of a second NPN bipolar transistor 214. A collectorterminal of the first transistor 212 may be coupled to a voltage supplyrail 216 via a third resistance 218 and a collector terminal of thesecond transistor 214 may be coupled to the voltage supply rail 216 viaa fourth resistance 220. An emitter terminal of the first transistor 212may be coupled to a collector terminal of a third NPN bipolar transistor222 via a fifth resistance 224. An emitter terminal of the thirdtransistor 222 may be coupled to a ground potential 226 via a sixthresistance 228. Similarly, an emitter terminal of the second transistor214 may be coupled to a collector terminal of a fourth NPN bipolartransistor 230 via a seventh resistance 232 An emitter terminal of thefourth transistor 230 may be coupled to the ground potential 226 via aneighth resistance 234. Base terminals of the third and fourthtransistors 222, 230 may be coupled together and to the ground potential226 via a first capacitance 236. The above-described circuitconfiguration including: the first to eighth resistances 208, 210, 218,220, 224, 228, 232, 234, the capacitance 236 and the first, second,third and fourth transistors 212, 214, 222, 230 constitute a bufferstage circuit.

A ground reference stage circuit of the driving stage circuit 200 maycomprise a fifth NPN bipolar transistor 238 and a sixth NPN bipolartransistor 240 arranged in a differential pair configuration. A baseterminal of the fifth transistor 238 may be coupled to the collectorterminal of the fourth transistor 230 and a base terminal of the sixthtransistor 240 may be coupled to the collector terminal of the thirdtransistor 222. A collector terminal of the fifth transistor 238 may becoupled to a drain terminal of a first P-channel Metal OxideSemiconductor Field Effect Transistor (MOSFET) 242; a source terminal ofthe first MOSFET 242 may be coupled to the supply rail 216. Similarly, acollector terminal of the sixth transistor 240 may be coupled to a drainterminal of a second P-channel MOSFET 244; a source terminal of thesecond MOSFET 244 may be coupled to the supply rail 216. A gate terminalof the first MOSFET 242 may be coupled to a gate terminal of the secondMOSFET 244. The gate terminals of the first and second MOSFETs 242, 244may also be coupled to the supply rail 216 via second capacitance 246.The gate terminals of the first and second MOSFETS 242, 244 may becoupled to a gate terminal of a third N-channel MOSFET 248 via a ninthresistance 250. The second and third MOSFETs may serve as a firstcurrent mirror. A source terminal of the third MOSFET 248 may be coupledto the supply rail 216 and a drain terminal of the third MOSFET 248 maybe coupled to a bias circuit 252. Emitter terminals of the fifth andsixth transistors 238, 240 may be coupled to a collector terminal of aseventh NPN bipolar transistor 254. An emitter terminal of the seventhtransistor 254 may be coupled to the ground potential 226 via a tenthresistance 256.

The collector terminal of the sixth transistor 240 may be coupled tofirst terminals of an eleventh resistance 260; a second terminal of theeleventh resistance 260 may be coupled to a collector terminal of aneighth NPN bipolar transistor 264 and to the ground potential via athird capacitance 266. A base terminal of the seventh transistor 264 maybe coupled to the collector terminal thereof. An emitter terminal of theseventh transistor 264 may be coupled to the ground potential via athirteenth resistance 268.

An amplifier circuit stage may comprise the first terminal of theeleventh resistance 260 being coupled to a base terminal of a ninth NPNbipolar transistor 270 via a fourteenth resistance 272. A first terminalof a twelfth resistance 262 may be coupled to the collector terminal ofthe fifth transistor 238 and a base terminal of a tenth NPN bipolartransistor 274 via a fifteenth resistance 276. A second terminal of thetwelfth resistance 262 may be coupled to the collector terminal of theeighth transistor 264. Collector terminals of the ninth and tenthtransistors 270, 274 may be coupled to the supply rail 216. An emitterterminal of the ninth transistor 270 may be coupled to a collectorterminal of an eleventh NPN bipolar transistor 278. An emitter terminalof the eleventh transistor 278 may be coupled to the ground potential226 via a sixteenth resistance 280. An emitter terminal of the tenthtransistor 274 may be coupled to a collector terminal of a twelfth NPNbipolar transistor 282. An emitter terminal of the twelfth transistor282 may be coupled to the ground potential 226 via a seventeenthresistance 284. Base terminals of the eleventh and twelfth transistors278, 282 may be coupled to the base terminals of the third, fourth andseventh transistors 222, 230, 254 and the bias circuit 252.

The emitter terminals of the ninth and tenth transistors 270, 274 may becoupled to the charge pump circuit 202. In this respect, the charge pumpcircuit 202 may comprise a thirteenth NPN bipolar transistor 286 and afourteenth NPN bipolar transistor 288 arranged in a differential pairconfiguration. A base terminal of the thirteenth transistor 286 may becoupled to the emitter terminal of the ninth transistor 270 and a baseterminal of the fourteenth transistor 288 may be coupled to the emitterterminal of the tenth transistor 274; the base terminals of thethirteenth transistor 286 and the fourteenth transistor 288 mayconstitute differential control terminals. Emitter terminals of thethirteenth and fourteenth transistors 286, 288 may be coupled to theground potential 226 via a pulsed current source 290; the pulsed currentsource may be coupled to the bias circuit 252.

A collector terminal of the thirteenth transistor 286 may be coupled toa trickle current supply rail 291 via an eighteenth resistance 292. Thecollector terminal of the thirteenth transistor 286 may also be coupledto the ground potential 226 via a fourth capacitance 294 and a fifthcapacitance 296 coupled in series. A collector terminal of thefourteenth transistor 288 may be coupled to a drain terminal of a fourthP-channel MOSFET 201. An output 211 for coupling to the low-pass filter104 may also be taken from the collector terminal of the fourteenthtransistor 288. A source terminal of the fourth MOSFET 201 may becoupled to the trickle current supply rail 291 via a trickle currentsource 203; the trickle current source 203 may be coupled to the biascircuit 252. A gate terminal of the fourth MOSFET 201 may be coupled toa potential divider. In this respect, the gate terminal of the fourthMOSFET 201 may be coupled to the ground potential 226 via a nineteenthresistance 205 and to the trickle current supply rail 291 via atwentieth resistance 207.

Referring to FIG. 3, the pulsed current source 290 may comprise afifteenth NPN bipolar transistor 300 that may have a collector terminalcoupled to a first coupling terminal 302 for coupling to the emitterterminals of the thirteenth and fourteenth transistors 286, 288. Anemitter of the fifteenth transistor 300 may be coupled to the groundpotential 226 via a twenty-first resistance 304. A base terminal of thefifteenth transistor 300 may be coupled to a base terminal of asixteenth NPN bipolar transistor 306. A collector terminal of thesixteenth transistor 306 may also be coupled to the first couplingterminal 302. An emitter terminal of the sixteenth transistor 306 may becoupled to the ground potential 226 via a twenty-second resistance 308.The base terminal of the sixteenth transistor 306 may also be coupled toa base terminal of a seventeenth NPN bipolar transistor 310 and theground potential 226 via a sixth capacitance 312. An emitter terminal ofthe seventeenth transistor 310 may be coupled to the ground potentialvia a twenty-third resistance 316.

A collector terminal of seventeenth transistor 310 may be coupled to agate terminal of a fifth N-channel MOSFET 316; a source terminal of thefifth MOSFET may be coupled to the ground potential 226 via atwenty-fourth resistance 318 and a drain terminal of the fifth MOSFET316 may be coupled to the supply rail 216 via a twenty-fifth resistance320. The collector terminal of the seventeenth transistor 310 may alsobe coupled to a drain terminal of a sixth P-channel MOSFET 322 via atwenty-sixth resistance 324. A source terminal of the sixth MOSFET 322may be coupled to a drain terminal of a seventh P-channel MOSFET 326; asource terminal of the seventh MOSFET 326 may be coupled to the supplyrail 216. A gate terminal of the sixth MOSFET 322 may be coupled to thebias circuit 252 and the gate terminal of the seventh MOSFET 326 may becoupled to the supply rail 216 via a seventh capacitance 328 and a gateterminal of an eighth P-channel MOSFET 330 via a twenty-seventhresistance 332. A source terminal of the eighth MOSFET 330 may becoupled to the supply rail 216 and a drain terminal of the eighth MOSFET330 may be coupled to the gate terminal thereof and to a bandgap currentgenerator 334.

Turning to the trickle current source 203, this circuit may comprise aninth P-channel MOSFET 336 that may have a drain terminal coupled to agate terminal thereof and the bandgap current generator 334. A sourceterminal of the ninth MOSFET 336 may be coupled to a source terminal ofa tenth P-channel MOSFET 338. A source terminal of the tenth MOSFET 338may be coupled to the trickle current supply rail 291 and the gateterminal of the tenth MOSFET 338 may be coupled to the drain terminalthereof and a gate terminal of an eleventh P-channel MOSFET 340 via atwenty-eighth resistance 342; the gate terminal of the eleventh MOSFET340 may also be coupled to the trickle current supply rail 291 via aneighth capacitance 344. A source terminal of the eleventh MOSFET 340 mayalso be coupled to the trickle current supply rail 291. A drain terminalof the eleventh MOSFET 340 may be coupled to a source terminal of atwelfth P-channel MOSFET 346; a drain terminal of the twelfth MOSFET 346may be coupled to a second coupling terminal 348 for coupling to thesource terminal of the fourth MOSFET 201. A gate terminal of the twelfthMOSFET 346 may be coupled to another potential divider. In this respect,the gate terminal of the twelfth MOSFET 346 may be coupled to thetrickle current supply rail 291 via a twenty-ninth resistance 350. Thegate terminal of the twelfth MOSFET 346 may also be coupled to acollector terminal of an eighteenth NPN bipolar transistor 352 via athirtieth resistance 354. An emitter terminal of the eighteenthtransistor 352 may be coupled to the ground potential 226 and the baseterminal of the eighteenth transistor 352 may be coupled to the biascircuit 252.

In operation, the PLL apparatus 100 may be powered up, usually as partof a larger circuit to serve a desired application, for example a radartransmitter. As the PLL apparatus 100 operates in a known manner forcharge pump PLLs, further explanation of the operation of the PLLapparatus 100 will not be described so as not to distract from the mainteachings of the examples of the invention set forth herein.

Turning to the charge pump apparatus 134 control signals are receivedfrom the phase and frequency detector 114 in the form of a firstdifferential down signal and a second differential down signalrespectively applied to the first down signal input 204 and the seconddown signal input 206 in response to input signals received by the phaseand frequency detector 114 from the divide-by-two frequency divider 132and the programmable frequency divider 112 during operation of the PLLapparatus 100. In this example, an up signal generation capability ofthe phase and frequency detector 114 is not used.

The first differential down signal and the second differential downsignal are Emitter-Coupled Logic (ECL) compliant signals. However, inorder to drive the charge pump circuit 202, the charge pump circuit 202may need to be provided with ground-referenced driving signals. As such,the driving stage circuit 200 may translate the first differential downsignal and the second differential down signal from being ECL compliantsignals to being ground-referenced signals. In this respect, the bufferstage circuit described above serves to shift the receivedground-referenced signal down to a lower level, for example about 0.7Vcorresponding to a voltage drop across a PN junction. Thereafter, thebuffered first differential down signal and the buffered seconddifferential down signal are converted to ground-referenced first andsecond differential down signals by the ground reference stage circuitdescribed above. The second and third MOSFETs 244, 248 constitute acurrent mirror that, in conjunction with the fifth and sixth transistors238, 240 arranged in the differential pair configuration, serve totranslate the ECL compliant signals to ground-referenced signals. Noisegenerated by the bias circuit 252 is supressed by the ninth resistance250 and the second capacitance 246, which operate together as a low-passfilter, thereby providing compliance with a noise specification for thePLL apparatus 100. Thereafter, the ground-referenced first and seconddifferential down signals are applied to the amplifier stage circuit inorder to amplify the ground-referenced first and second differentialdown signals prior to application at the charge pump circuit 202, namelyat the base terminals of the thirteenth and fourteenth transistors 286,288. The amplification may be required in order to drive the pulsedcurrent source 290.

Turning to the charge pump circuit 202, the differential pairconfiguration provides a first branch that comprises a second low-passfilter formed from the eighteenth resistance 292 and the fourth andfifth capacitances 294, 296. The first branch serves as “dummy” path inorder to avoid charge injection into a second branch provided by thedifferential pair configuration and comprising the trickle currentsource 203. The provision of the trickle current source 203 may enablethe locking operation of the charge pump PLL. Noise from the tricklecurrent generated by the trickle current source 203 may be filtered outto comply with a noise specification of the PLL. This is achieved bymaintaining a constant DC ratio between the trickle current generated bythe trickle current source 203 and the pulsed current source 290. Thepulsed current source 290 is pulsed by application of the amplifiedground-referenced first and second differential signals provided by thedriving circuit 200 to drive the thirteenth and fourteenth transistors286, 288 of the differential pair configuration. An output signal isthen provided at the output 211, which is applied to the low-pass filter104 of FIG. 1.

Turning to the pulsed current source 290 and the trickle current source203 of FIG. 3, the pulsed current source 290 may comprise a secondcurrent mirror formed by the seventh and eighth MOSFETs 326, 330. Thepulsed current source may also comprise a third current mirror formedfrom the fifteenth, sixteen and seventeenth transistors 300, 306, 310.The bandgap current generator 334 may generate a constant current thatis invariant over a given temperature range, for example a temperaturerange associated with an automotive vehicle. However, in order tosuppress noise from the bandgap current generator 334, the secondcurrent mirror may comprise a third low-pass filter formed by theseventh capacitor 328 and the twenty-seventh resistance 332. Inoperation, current may be generated using the sixth, seventh and eighthMOSFETs 322, 326, 330 under the control of the bias circuit 252. Thefifteenth, sixteenth and seventeenth bipolar transistors 300, 306, 310are employed in order to reduce the output capacitance of the secondcurrent mirror.

In operation, the pulsed current source 290 generates a logic HIGHoutput current signal in response to a ground-referenced signalgenerated by the circuit 200 being at a logic HIGH level, and a logicLOW output current signal when the ground-referenced signal generated bythe circuit 200 is at a logic LOW level, i.e. the output generated bythe pulsed current source 290 follows the ground-referenced signal ofthe-circuit 200.

The trickle current source 203 may comprise a fourth current mirrorformed from the tenth and eleventh MOSFETs 338, 340. Again, in order tosuppress noise from the bandgap current generator 334, the fourthcurrent mirror may comprise a fourth low-pass filter formed by theeighth capacitance 344 and the twenty-eighth resistance 342. Inoperation, current may be generated using the tenth, eleventh andtwelfth MOSFETs 338, 340, 346 operating with a 5V supply voltage andunder the control of the bias circuit 252. The trickle current may be apredetermined constant current.

The trickle current source 203 and the pulsed current source 290 arecontrolled by a DAC of the bias circuit 252, for example a 6 bit DAC,which may generate the ground-referenced current in order to calibratethe bandwidth of the PLL apparatus 100.

It is thus possible to provide a charge pump circuit, phase locked loopapparatus, and integrated circuit that are capable of supporting highspeed operation whilst exhibiting very low noise characteristics over awide tuning range at a relatively high voltage range, for examplebetween about 0.5 V and about 5V. The use of a BICMOS implementation forboth the driving stage circuit 200 and the charge pump circuit 202assists in the provision of these benefits. The slew rate of currentsignals provided at the output of the charge pump circuit are alsoimproved.

Of course, the above advantages are examples, and these or otheradvantages may be achieved by the examples set forth herein. Further,the skilled person will appreciate that not all advantages stated aboveare necessarily achieved by embodiments described herein.

In the foregoing specification, the invention has been described withreference to specific examples of embodiments of the invention. It will,however, be evident that various modifications and changes may be madetherein without departing from the broader scope of the invention as setforth in the appended claims.

Those skilled in the art will recognize that the boundaries betweenlogic blocks are merely illustrative and that alternative embodimentsmay merge logic blocks or circuit elements or impose an alternatedecomposition of functionality upon various logic blocks or circuitelements. Thus, it is to be understood that the architectures depictedherein are merely exemplary, and that in fact many other architecturescan be implemented which achieve the same functionality. For example,blocks set forth in FIG. 1 can be combined depending upon designconvenience and the topology set forth in these figures is not intendedto be limiting in any way.

References made herein to “transistors” should be understood to beembrace any suitable switching device. Likewise, references to gateterminals and base terminals herein should be understood to extend toreferences to any suitable control terminal.

Although certain families of switching device, for example NPNtransistors and P-channel FETs have been used herein for exemplarypurposes and the skilled person will readily understand thatcomplementary technologies may be employed, for example PNP transistorsand N-channel FETs.

Any arrangement of components to achieve the same functionality iseffectively “associated” such that the desired functionality isachieved. Hence, any two components herein combined to achieve aparticular functionality can be seen as “associated with” each othersuch that the desired functionality is achieved, irrespective ofarchitectures or intermedial components. Likewise, any two components soassociated can also be viewed as being “operably connected,” or“operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundariesbetween the functionality of the above described operations are merelyillustrative. The functionality of multiple operations may be combinedinto a single operation, and/or the functionality of a single operationmay be distributed in additional operations. Moreover, alternativeembodiments may include multiple instances of a particular operation,and the order of operations may be altered in various other embodiments.

The examples set forth herein, or portions thereof, may be implementedas soft or code representations of physical circuitry or of logicalrepresentations convertible into physical circuitry, such as in ahardware description language of any appropriate type.

Also, the embodiments set forth herein are not limited to physicaldevices or units implemented in non-programmable hardware but can alsobe applied in programmable devices or units able to perform the desireddevice functions by operating in accordance with suitable programnon-transitory code, such as mainframes, minicomputers, servers,workstations, personal computers, notepads, personal digital assistants,commonly denoted as ‘computer systems’.

Other modifications, variations and alternatives to the examples setforth herein are also possible. The specifications and drawings are,accordingly, to be regarded in an illustrative rather than in arestrictive sense.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word ‘comprising’ does notexclude the presence of other elements or steps then those listed in aclaim. Furthermore, the terms “a” or “an,” as used herein, are definedas one or more than one. Also, the use of introductory phrases such as“at least one” and “one or more” in the claims should not be construedto imply that the introduction of another claim element by theindefinite articles “a” or “an” limits any particular claim containingsuch introduced claim element to inventions containing only one suchelement, even when the same claim includes the introductory phrases “oneor more” or “at least one” and indefinite articles such as “a” or “an.”The same holds true for the use of definite articles. Unless statedotherwise, terms such as “first” and “second” are used to arbitrarilydistinguish between the elements such terms describe. Thus, these termsare not necessarily intended to indicate temporal or otherprioritization of such elements. The mere fact that certain measures arerecited in mutually different claims does not indicate that acombination of these measures cannot be used to advantage.

1. An apparatus comprising: a first bipolar transistor device and asecond bipolar switching device arranged in a differential pairconfiguration; a first terminal of each of the first and second bipolarswitching devices coupled to a voltage supply; a second like terminal ofeach of the first and second bipolar switching devices being coupledtogether and to ground potential via a pulsed current source; and afield effect switching device; wherein the first terminal of the firstbipolar switching device is coupled to the voltage supply via the fieldeffect switching device.
 2. An apparatus as claimed in claim 1, whereinthe first terminal of the second bipolar switching device is coupled tothe voltage supply via a low pass filter.
 3. An apparatus as claimed inclaim 1, wherein the first terminal of the first bipolar switchingdevice is also coupled to the supply via another current source.
 4. Anapparatus as claimed in claim 3, wherein the field effect switchingdevice is coupled to the voltage supply via the another current source.5. An apparatus as claimed in claim 1, wherein the first and secondbipolar switching devices each comprise a control terminal, togetherconstituting differential control terminals.
 6. An apparatus as claimedin claim 1, further comprising: a driving stage circuit coupled to thecharge pump circuit and arranged to translate, when in use, an emittercoupled logic signal to a ground-referenced signal.
 7. An apparatus asclaimed in claim 6, wherein the driving stage circuit comprises a buffercircuit.
 8. An apparatus as claimed in claim 7, wherein the drivingstage circuit comprises a ground-reference signal generation circuitcoupled to the buffer circuit.
 9. An apparatus as claimed in claim 8,wherein the driving stage circuit comprises an amplifier circuit coupledto the ground-reference signal generation circuit.
 10. An apparatus asclaimed in claim 1, wherein the charge pump circuit is implemented in aphase locked loop.
 11. An apparatus as claim in claim 6, wherein thecharge pump circuit is implemented in a phase locked loop apparatus. 12.An apparatus as claimed in claim 11, further comprising: a phase andfrequency detector coupled to the driving stage circuit.
 13. Anapparatus as claimed in claim 12, further comprising: a low-pass filtercoupled to the charge pump circuit and a voltage controlled oscillator.14. An apparatus as claimed in claim 13, further comprising: a staticfrequency divider coupled to the voltage controlled oscillator.
 15. Anapparatus as claimed in claim 14, further comprising: a programmablefrequency divider; a digital controller having a reference frequencyinput and a control output, the control output being coupled to theprogrammable frequency divider; wherein the programmable frequencydivider is coupled between the static frequency divider and the phaseand frequency detector.
 16. An apparatus as claimed in claim 15, furthercomprising: a reference frequency generator coupled to the digitalcontroller and the phase and frequency detector.
 17. An apparatus asclaimed in claim 16, wherein the reference frequency generator iscoupled to the phase and frequency detector via a frequency divider. 18.An apparatus as claim in claim 1, wherein the apparatus is implementedin a radar apparatus.
 19. (canceled)
 20. A method of manufacturing acharge pump circuit, the method comprising: providing and arranging afirst bipolar transistor device and a second bipolar switching device ina differential pair configuration; coupling a first terminal of each ofthe first and second bipolar switching devices to a voltage supply;coupling a second like terminal of each of the first and second bipolarswitching devices together and to ground potential via a pulsed currentsource; and coupling the first terminal of the first bipolar switchingdevice to the voltage supply via a field effect switching device.